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i coupler digital isolator data sheet adum1100 rev. i information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2001C2012 analog devices, inc. all rights reserved. features high data rate: dc to 100 mbps (nrz) compatible with 3.3 v and 5.0 v operation/level translation 125c maximum operating temperature low power operation 5 v operation 1.0 ma maximum @ 1 mbps 4.5 ma maximum @ 25 mbps 16.8 ma maximum @ 100 mbps 3.3 v operation 0.4 ma maximum @ 1 mbps 3.5 ma maximum @ 25 mbps 7.1 ma maximum @ 50 mbps 8-lead soic_n package (rohs compliant version available) high common-mode transient immunity: >25 kv/s safety and regulatory approvals ul recognized 2500 v rms for 1 minute per ul 1577 csa component acceptance notice #5a vde certificate of conformity din v vde v 0884-10 (vde v 0884-10):2006-12 v iorm = 560 v peak applications digital field bus isolation opto-isolator replacement computer peripheral interface microprocessor system interface general instrumentation and data acquisition applications general description the adum1100 1 is a digital isolator based on analog devices inc. , i coupler? technology. combining high speed cmos and mono lith ic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives, such as optocoupler devices. configured as a pin-compatible replacement for existing high speed optocouplers, the adum1100 supports data rates as high as 25 mbps and 100 mbps. the adum1100 operates with a voltage supply ranging from 3.0 v to 5.5 v, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125c. it operates at very low power, less than 0.9 ma of quiescent current (sum of both sides), and a dynamic current of less than 160 a per mbps of data rate. unlike other optocoupler alternatives, the adum1100 provides dc correctness with a patented refresh feature that continuously updates the output signal. the adum1100 is offered in three grades. the adum1100ar and adum1100br can operate up to a maximum temperature of 105c and support data rates up to 25 mbps and 100 mbps, respectively. the adum1100ur can operate up to a maximum temperature of 125c and supports data rates up to 100 mbps. 1 protected by u.s. patents 5, 952,849; 6,525,566; 6,922,080; 6,903,578; 6,873,065; 7,075,329. functional block diagram watchdog e n c o d e d e c o d e update v dd1 v i (data in) v dd1 gnd 1 v dd2 gnd 2 v o (data out) gnd 2 adum1100 notes 1. for principles of operation, see method of operation, dc correctness, and magnetic field immunity section. 8 7 6 5 1 2 3 4 02462-001 figure 1.
adum1100 data sheet rev. i | page 2 of 20 table of contents features .............................................................................................. 1 ? applications....................................................................................... 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 3 ? specifications..................................................................................... 4 ? electrical specifications5 v operation ................................. 4 ? electrical specifications3.3 v operation .............................. 6 ? electrical specificationsmixed 5 v/3 v or 3 v/5 v operation....................................................................................... 8 ? package characteristics ............................................................. 10 ? regulatory information............................................................. 10 ? insulation and safety-related specifications.......................... 10 ? din v vde v 0884-10 (vde v 0884-10):2006-12 insulation characteristics.......................................................... 11 ? recommended operating conditions .................................... 11 ? absolute maximum ratings ......................................................... 12 ? esd caution................................................................................ 12 ? pin configuration and function descriptions........................... 13 ? typical performance characteristics ........................................... 14 ? application information................................................................ 16 ? pc board layout ........................................................................ 16 ? propagation delay-related parameters................................... 16 ? method of operation, dc correctness, and magnetic field immunity ........................................................................... 17 ? power consumption .................................................................. 18 ? outline dimensions ....................................................................... 19 ? ordering guide .......................................................................... 19 ?
data sheet adum1100 rev. i | page 3 of 20 revision history 3/12rev. h to rev. i created hyperlink for safety and regulatory approvals entry in features section ................................................................. 1 change to pc board layout section ............................................ 16 3/11rev. g to rev. h changes to data sheet title ............................................................. 1 changes to ordering guide ........................................................... 18 6/07rev. f to rev. g updated vde certification throughout ....................................... 1 changes to features and endnote 1 ................................................ 1 changes to table 5 and table 6 ....................................................... 9 updated outline dimensions ....................................................... 18 changes to ordering guide .......................................................... 18 3/06rev. e to rev. f updated format .................................................................. universal added note 1 ..................................................................................... 1 changes to table 1 ............................................................................ 4 changes to table 2 ............................................................................ 6 changes to table 3 ............................................................................ 8 added table 11 ................................................................................ 13 inserted power consumption section .......................................... 18 10/03rev. d to rev. e changes to product name, features, and general description . 1 changes to regulatory information ............................................... 6 changes to din en 60747-5-2 (vde 0884 part 2) insulation characteristics ................................................................................... 6 changes to absolute maximum ratings ........................................ 7 changes to recommended operating conditions ....................... 7 changes to ordering guide ............................................................. 8 6/03rev. c to rev. d changed din en 60747-5-2 (vde 0884 part 2) insulation characteristics ................................................................................... 6 updated ordering guide ................................................................. 8 updated outline dimensions ........................................................ 13 4/03rev. b to rev. c changes to features and patent note ............................................. 1 changes to regulatory information ............................................... 6 changes to insulation characteristics section .............................. 6 changes to absolute maximum ratings........................................ 7 changes to package branding ......................................................... 8 changes to method of operation, dc correctness, and magnetic field immunity section ................................................ 11 replaced figure 9 ............................................................................ 12 1/03rev. a to rev. b added adum1100ur grade ........................................... universal changed adum1100ar/adum1100br to adum1100 ......................................................................... universal changes to features and general description .............................. 1 changes to specifications ................................................................ 2 added electrical specifications, mixed 5 v/3 v or 3 v/5 v operation table ................................................................................. 4 updated regulatory information ................................................... 6 changes to vde 0884 insulation characteristics ........................ 6 changes to absolute maximum ratings........................................ 7 changes to package branding ......................................................... 8 updated tpc 3 to tpc 8 ................................................................. 9 deleted i coupler in field bus networks section ....................... 11 changes to figure 8 ........................................................................ 12 added figure 9 and related text .................................................. 12 11/02rev. 0 to rev. a edits to features ................................................................................ 1 edits to regulatory information ..................................................... 4 edits to vde 0884 insulation characteristics ............................... 5 added revision history ................................................................. 12 updated outline dimensions ........................................................ 12
data sheet adum1100 rev. i | page 4 of 20 specifications electrical specifications5 v operation all voltages are relative to their respective ground. 4.5 v v dd1 5.5 v, 4.5 v v dd2 5.5 v. all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dd2 = 5 v. table 1. parameter symbol min typ max unit test conditions dc specifications input supply current i dd1 (q) 0.3 0.8 ma v i = 0 v or v dd1 output supply current i dd2 (q) 0.01 0.06 ma v i = 0 v or v dd1 input supply current (25 mbps) (see figure 5 ) i dd1 (25) 2.2 3.5 ma 12.5 mhz logic signal frequency output supply current 1 (25 mbps) (see figure 6 ) i dd2 (25) 0.5 1.0 ma 12.5 mhz logic signal frequency input supply current (100 mbps) (see figure 5 ) i dd1 (100) 9.0 14 ma 50 mhz logic signal frequency, adum1100br/adum1100ur only output supply current 1 (100 mbps) (see figure 6 ) i dd2 (100) 2.0 2.8 ma 50 mhz logic signal frequency, adum1100br/adum1100ur only input current i i ?10 +0.01 +10 a 0 v v in v dd1 logic high output voltage v oh v dd2 ? 0.1 5.0 v i o = ?20 a, v i = v ih v dd2 ? 0.8 4.6 v i o = ?4 ma, v i = v ih logic low output voltage v ol 0.0 0.1 v i o = 20 a, v i = v il 0.03 0.1 v i o = 400 a, v i = v il 0.3 0.8 v i o = 4 ma, v i = v il switching specifications for adum1100ar minimum pulse width 2 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 3 25 mbps c l = 15 pf, cmos signal levels for adum1100br/adum1100ur minimum pulse width 2 pw 6.7 10 ns c l = 15 pf, cmos signal levels maximum data rate 3 100 150 mbps c l = 15 pf, cmos signal levels for all grades propagation delay time to logic low output 4 , 5 (see figure 7 ) t phl 10.5 18 ns c l = 15 pf, cmos signal levels propagation delay time to logic high output 4 , 5 (see figure 7 ) t plh 10.5 18 ns c l = 15 pf, cmos signal levels pulse width distortion |t plh ? t phl | 5 pwd 0.5 2 ns c l = 15 pf, cmos signal levels change vs. temperature 6 3 ps/c c l = 15 pf, cmos signal levels propagation delay skew (equal temperature) 5 , 7 t psk1 8 ns c l = 15 pf, cmos signal levels propagation delay skew (equal temperature, supplies) 5 , 7 t psk2 6 ns c l = 15 pf, cmos signal levels output rise/fall time t r , t f 3 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic low/high output 8 |cm l |, |cm h | 25 35 kv/s v i = 0 v or v dd1 , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.2 mbps input dynamic supply current 9 i ddi (d) 0.09 ma/mbps output dynamic supply current 9 i ddo (d) 0.02 ma/mbps
data sheet adum1100 rev. i | page 5 of 20 1 output supply current values are with no output load prese nt. see and for information on supply current vari ation with logic signal frequency. see the section for guidance on calculating the in put and output supply currents fo r a given data rate and output load. figure 5 fig ure 5 figure 6 figure 6 power consumption power consumption 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl is measured from the 50% level of the falling edge of the v i signal to the 50% level of the falling edge of the v o signal. t plh is measured from the 50% level of the rising edge of the v i signal to the 50% level of the rising edge of the v o signal. 5 because the input thresholds of the adum1100 are at voltages othe r than the 50% level of typical input signals, the measured p ropagation delay and pulse width distortion can be affected by slow input rise/fall times. see the section and th rough for information on the impact of given input rise/fall times on these parameters. propagatio n delay-related parameters figure 14 figure 18 6 pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1c change i n operating temperature. 7 t psk1 is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure and output load within the recommended operat ing conditions. t psk2 is the magnitude of the worst-case difference in t phl and/or t plh that is measured between un its at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew ra tes apply to both rising and falling edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see and for information on supply current variation with logic signal fr equency. see the section for guidance on calculating the input a nd output supply currents for a given data rate and output load.
adum1100 data sheet rev. i | page 6 of 20 electrical specifications3.3 v operation all voltages are relative to their respective ground. 3.0 v v dd1 3.6 v, 3.0 v v dd2 3.6 v. all minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. all typical specifications are at t a = 25c, v dd1 = v dd2 = 3.3 v. table 2. parameter symbol min typ max unit test conditions dc specifications input supply current i dd1 (q) 0.1 0.3 ma v i = 0 v or v dd1 output supply current i dd2 (q) 0.005 0.04 ma v i = 0 v or v dd1 input supply current (25 mbps) (see figure 5 ) i dd1 (25) 2.0 2.8 ma 12.5 mhz logic signal frequency output supply current 1 (25 mbps) (see figure 6 ) i dd2 (25) 0.3 0.7 ma 12.5 mhz logic signal frequency input supply current (50 mbps) (see figure 5 ) i dd1 (50) 4.0 6.0 ma 25 mhz logic signal frequency, adum1100br/adum1100ur only output supply current 1 (50 mbps) (see figure 6 ) i dd2 (50) 1.2 1.6 ma 25 mhz logic signal frequency, adum1100br/adum1100ur only input current i i ?10 +0.01 +10 a 0 v v in v dd1 logic high output voltage v oh v dd2 ? 0.1 3.3 v i o = ?20 a, v i = v ih v dd2 ? 0.5 3.0 v i o = ?2.5 ma, v i = v ih logic low output voltage v ol 0.0 0.1 v i o = 20 a, v i = v ih 0.04 0.1 v i o = 400 a, v i = v ih 0.3 0.4 v i o = 2.5 ma, v i = v ih switching specifications for adum1100ar minimum pulse width 2 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 3 25 mbps c l = 15 pf, cmos signal levels for adum1100br/adum1100ur minimum pulse width 2 pw 10 20 ns c l = 15 pf, cmos signal levels maximum data rate 3 50 100 mbps c l = 15 pf, cmos signal levels for all grades propagation delay time to logic low output 4 , 5 (see figure 8 ) t phl 14.5 28 ns c l = 15 pf, cmos signal levels propagation delay time to logic high output 4 , 5 (see figure 8 ) t plh 15.0 28 ns c l = 15 pf, cmos signal levels pulse width distortion |t plh ? t phl | 5 pwd 0.5 3 ns c l = 15 pf, cmos signal levels change vs. temperature 6 10 ps/c c l = 15 pf, cmos signal levels propagation delay skew (equal temperature) 5 , 7 t psk1 15 ns c l = 15 pf, cmos signal levels propagation delay skew (equal temperature, supplies) 5 , 7 t psk2 12 ns c l = 15 pf, cmos signal levels output rise/fall time t r , t f 3 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic low/high output 8 |cm l |, |cm h | 25 35 kv/s v i = 0 v or v dd1 , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 1.1 mbps input dynamic supply current 9 i ddi (d) 0.08 ma/mbps output dynamic supply current 9 i ddo (d) 0.04 ma/mbps
data sheet adum1100 rev. i | page 7 of 20 1 output supply current values are with no output load prese nt. see and for information on supply current vari ation with logic signal frequency. see the section for guidance on calculating the in put and output supply currents fo r a given data rate and output load. figure 5 fig ure 5 figure 6 figure 6 power consumption power consumption 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl is measured from the 50% level of the falling edge of the v i signal to the 50% level of the falling edge of the v o signal. t plh is measured from the 50% level of the rising edge of the v i signal to the 50% level of the rising edge of the v o signal. 5 because the input thresholds of the adum1100 are at voltages othe r than the 50% level of typical input signals, the measured p ropagation delay and pulse width distortion can be affected by slow input rise/fall times. see the section and th rough for information on the impact of given input rise/fal l times on these parameters. propagatio n delay-related parameters figure 14 figure 18 6 pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1c change i n operating temperature. 7 t psk1 is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure and output load within the recommended operat ing conditions. t psk2 is the magnitude of the worst-case difference in t phl and/or t plh that is measured between un its at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew ra tes apply to both rising and falling edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see and for information on supply current variation with logic signal fr equency. see the section for guidance on calculating the input a nd output supply currents for a given data rate and output load.
adum1100 data sheet rev. i | page 8 of 20 electrical specificationsmixed 5 v/3 v or 3 v/5 v operation all voltages are relative to their respective ground. 5 v/3 v operation: 4.5 v v dd1 5.5 v, 3.0 v v dd2 3.6 v. 3 v/5 v operation: 7 v dd1 3.6 v, 4.5 v v dd2 5.5 v. all minimum/maximum specifications apply over the entire recommended operation range, vomftt otherwise noted. all typical specifications are at t a = 25c, v dd1 = 3.3 v, v dd2 = 5 v or v dd1 = 5 v, v dd2 = 3.3 v. table 3. parameter symbol min typ max unit test conditions dc specifications input supply current, quiescent i ddi (q) 5 v/3 v operation 0.3 0.8 ma 3 v/5 v operation 0.1 0.3 ma output supply current, quiescent i ddo (q) 5 v/3 v operation 0.005 0.04 ma 3 v/5 v operation 0.01 0.06 ma input supply current, 25 mbps i ddi (25) 5 v/3 v operation 2.2 3.5 ma 12.5 mhz logic signal frequency 3 v/5 v operation 2.0 2.8 ma 12.5 mhz logic signal frequency output supply current 1 , 25 mbps i ddo (25) 5 v/3 v operation 0.3 0.7 ma 12.5 mhz logic signal frequency 3 v/5 v operation 0.5 1.0 ma 12.5 mhz logic signal frequency input supply current, 50 mbps i ddi (50) 5 v/3 v operation 4.5 7.0 ma 25 mhz logic signal frequency 3 v/5 v operation 4.0 6.0 ma 25 mhz logic signal frequency output supply current 1 , 50 mbps i ddo (50) 5 v/3 v operation 1.2 1.6 ma 25 mhz logic signal frequency 3 v/5 v operation 1.0 1.5 ma 25 mhz logic signal frequency input currents i ia ?10 +0.01 +10 a 0 v v ia , v ib , v ic , v id v dd1 or v dd2 logic high output voltage v oh v dd2 ? 0.1 3.3 v i o = ?20 a, v i = v ih 5 v/3 v operation v dd2 ? 0.5 3.0 v i o = ?2.5 ma, v i = v ih logic low output voltage v ol 0.0 0.1 v i o = 20 a, v i = v il 5 v/3 v operation 0.04 0.1 v i o = 400 a, v i = v il 0.3 0.4 v i o = 2.5 ma, v i = v il logic high output voltage v oh v dd2 ? 0.1 5.0 v i o = ?20 a, v i = v ih 3 v/5 v operation v dd2 ? 0.8 4.6 v i o = ?4 ma, v i = v ih logic low output voltage v ol 0.0 0.1 v i o = 20 a, v i = v il 3 v/5 v operation 0.03 0.1 v i o = 400 a, v i = v il 0.3 0.8 v i o = 4 ma, v i = v il switching specifications for adum1100ar minimum pulse width 2 pw 40 ns c l = 15 pf, cmos signal levels maximum data rate 3 25 mbps c l = 15 pf, cmos signal levels for adum1100br/adum1100ur minimum pulse width 2 pw 20 ns c l = 15 pf, cmos signal levels maximum data rate 3 50 mbps c l = 15 pf, cmos signal levels for all grades propagation delay time to logic low/high output 4 , 5 t phl , t plh 5 v/3 v operation (see figure 9 ) 13 21 ns c l = 15 pf, cmos signal levels 3 v/5 v operation (see figure 10 ) 16 26 ns c l = 15 pf, cmos signal levels
data sheet adum1100 rev. i | page 9 of 20 parameter symbol min typ max unit test conditions pulse width distortion, |t plh ? t phl | 5 pwd 5 v/3 v operation 0.5 2 ns c l = 15 pf, cmos signal levels 3 v/5 v operation 0.5 3 ns c l = 15 pf, cmos signal levels change in pulse width distortion vs. temperature 6 5 v/3 v operation 3 ps/c c l = 15 pf, cmos signal levels 3 v/5 v operation 10 ps/c c l = 15 pf, cmos signal levels propagation delay skew (equal temperature) 5 , 7 t psk1 5 v/3 v operation 12 ns c l = 15 pf, cmos signal levels 3 v/5 v operation 15 ns c l = 15 pf, cmos signal levels propagation delay skew (equal temperature, supplies) 5 , 7 t psk2 5 v/3 v operation 9 ns c l = 15 pf, cmos signal levels 3 v/5 v operation 12 ns c l = 15 pf, cmos signal levels output rise/fall time (10% to 90%) t r , t f 3 ns c l = 15 pf, cmos signal levels common-mode transient immunity at logic low/high output 8 |cm l |, |cm h | 25 35 kv/s v i = 0 v or v dd1 , v cm = 1000 v, transient magnitude = 800 v refresh rate f r 5 v/3 v operation 1.2 mbps 3 v/5 v operation 1.1 mbps input dynamic supply current 9 c pd1 5 v/3 v operation 0.09 ma/mbps 3 v/5 v operation 0.08 ma/mbps output dynamic supply current 9 c pd2 5 v/3 v operation 0.04 ma/mbps 3 v/5 v operation 0.02 ma/mbps 1 output supply current values are with no output load prese nt. see and for information on supply current vari ation with logic signal frequency. see the section for guidance on calculating the in put and output supply currents fo r a given data rate and output load. figure 5 fig ure 5 figure 6 figure 6 power consumption power consumption 2 the minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 the maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 t phl is measured from the 50% level of the falling edge of the v i signal to the 50% level of the falling edge of the v o signal. t plh is measured from the 50% level of the rising edge of the v i signal to the 50% level of the rising edge of the v o signal. 5 because the input thresholds of the adum1100 are at voltages othe r than the 50% level of typical input signals, the measured p ropagation delay and pulse width distortion can be affected by slow input rise/fall times. see the section and th rough for information on the impact of given input rise/fal l times on these parameters. propagatio n delay-related parameters figure 14 figure 18 6 pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1c change i n operating temperature. 7 t psk1 is the magnitude of the worst-case difference in t phl and/or t plh that is measured between units at the same operating temperat ure and output load within the recommended operat ing conditions. t psk2 is the magnitude of the worst-case difference in t phl and/or t plh that is measured between un its at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 cm h is the maximum common-mode voltage slew rate that can be sustained while maintaining v o > 0.8 v dd2 . cm l is the maximum common-mod e voltage slew rate that can be sustained while maintaining v o < 0.8 v. the common-mode voltage slew ra tes apply to both rising and falling edges. the transient magnitude is the range over which the common mode is slewed. 9 dynamic supply current is the incremental amou nt of supply current required for a 1 mbps increase in signal data rate. see and for information on supply current variation with logic signal fr equency. see the section for guidance on calculating the input a nd output supply currents for a given data rate and output load.
adum1100 data sheet rev. i | page 10 of 20 package characteristics table 4. parameter symbol min typ max unit test conditions resistance (input-to-output) 1 r i-o 10 12 capacitance (input-to-output) 1 c i-o 1.0 pf f = 1 mhz input capacitance 2 c i 4.0 pf ic junction-to-case thermal resistance, side 1 jci 46 c/w ic junction-to-case thermal resistance, side 2 jco 41 c/w thermocouple located at center of package underside package power dissipation p pd 240 mw 1 the device is considered a 2-terminal device; pin 1, pin 2, pin 3, and pin 4 are shorted together, and pin 5, pin 6, pin 7, an d pin 8 are shorted together. 2 input capacitance is measured at pin 2 (v i ). regulatory information the adum1100 is approved by the following organizations. table 5. ul csa vde recognized under 1577 component recognition program 1 approved under csa component acceptance notice #5a certified according to din v vde v 0884-10 (vde v 0884-10):2006-12 2 single/basic insulation, 2500 v rms isolation voltage basic insulation per csa 60950-1-03 and iec 60950-1, 400 v rms (565 v peak) maximum working voltage reinforced insulation, 560 v peak file e214100 file 205078 file 2471900-4880-0001 1 in accordance with ul 1577, each adum1100 is proof tested by applying an insulation test voltage 3000 v rms for 1 sec (curren t leakage detection limit = 5 a). 2 in accordance with din v vde v 0884-10, each adum1100 is proof tested by applying an insulation test voltage 1050 v peak for 1 sec (partial discharge detection limit = 5 pc). the * marking branded on the component designates din v vde v 0884-10 approval. insulation and safety-related specifications table 6. parameter symbol value unit conditions minimum external air gap (clearance) l(i01) 4.90 min mm measured from input termin als to output terminals, shortest distance through air minimum external tracking (creepage) l(i02) 4.01 min mm measured from input termin als to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.016 min mm insulation distance through insulation tracking resistance (comparative tracking index) cti >175 v din iec 112/vde 0303 part 1 isolation group iiia material group (din vde 0110, 1/89, table i) maximum working voltage compatible with 50 years service life v iorm 565 v peak continuous peak voltage across the isolation barrier
data sheet adum1100 rev. i | page 11 of 20 din v vde v 0884-10 (vde v 0884-10):2006-12 insulation characteristics this isolator is suitable for reinforced isolation only within the safety limit data. maintenance of the safety data is ensure d by means of pro tective circuits. the asterisk (*) marking on the package denotes din v vde v 0884-10 approval for 560 v peak working voltag e. table 7. description conditions symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 150 v rms i to iv for rated mains voltage 300 v rms i to iii for rated mains voltage 400 v rms i to ii climatic classification 40/105/21 pollution degree per din vde 0110, table 1 2 maximum working insulation voltage v iorm 560 v peak input-to-output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 sec, partial discharge < 5 pc v pr 1050 v peak input-to-output test voltage, method a v iorm 1.6 = v pr , t m = 60 sec, partial discharge < 5 pc v pr after environmental tests subgroup 1 896 v peak after input and/or safety test subgroup 2 and subgroup 3 v iorm 1.2 = v pr , t m = 60 sec, partial discharge < 5 pc 672 v peak highest allowable overvoltage transient overvoltage, t tr = 10 seconds v tr 4000 v peak safety-limiting values maximum va lue allowed in the event of a failure (see figure 2 ) case temperature t s 150 c side 1 current i s1 160 ma side 2 current i s2 170 ma insulation resistance at t s v io = 500 v r s >10 9 case temperature (c) 180 0 safety-limiting current (ma) 100 80 0 50 100 150 200 120 160 140 20 40 60 input current output current 02462-002 figure 2. thermal derating curve, dependence of safety-limiting values with case temperature per din v vde v 0884-10 recommended operat ing conditions table 8. parameter symbol min max unit operating temperature adum1100ar/adum1100br t a ?40 +105 c adum1100ur t a ?40 +125 c supply voltages 1 v dd1 , v dd2 3.0 5.5 v logic high input voltage, 5 v operation 1 , 2 (see figure 11 and figure 12 ) v ih 2.0 v dd1 v logic low input voltage, 5 v operation 1 , 2 (see figure 11 and figure 12 ) v il 0.0 0.8 v logic high input voltage, 3.3 v operation 1 , 2 (see figure 11 and figure 12 ) v ih 1.5 v dd1 v logic low input voltage, 3.3 v operation 1 , 2 (see figure 11 and figure 12 ) v il 0.0 0.5 v input signal rise and fall times 1.0 ms 1 all voltages are relative to their respective ground. 2 input switching thresholds have 300 mv of hysteresis. see the section, , and figure 20 for information on immuni ty to external magnetic fields. method of operation, dc correctness, and magnetic field immuni ty figure 19
adum1100 data sheet rev. i | page 12 of 20 absolute maximum ratings table 9. parameter symbol min max unit storage temperature t st ?55 +150 c ambient operating temperature t a ?40 +125 c supply voltages 1 v dd1 , v dd2 ?0.5 +6.5 v input voltage 1 v i ?0.5 v dd1 + 0.5 v output voltage 1 v o ?0.5 v dd2 + 0.5 v average current, per pin 2 temperature 105c ?25 +25 ma temperature 125c input current ?7 +7 ma output current ?20 +20 ma common-mode transients 3 ?100 +100 kv/s 1 all voltages are relative to their respective ground. 2 see figure 2 for information on maximum a llowable current for various temperatures. 3 refers to common-mode transients across the insulation barrier. common-mode transients exceeding the absolute maximum rating may cause latch-up or permanent damage. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution table 10. truth table (positive logic) v i input v dd1 state v dd2 state v o output h powered powered h l powered powered l x unpowered powered h 1 x powered unpowered x 1 1 v o returns to v i state within 1 s of power restoration. figure 3 shows the package branding. the asterisk (*) is the din en 60747-5-2 mark, r is the package designator (r denotes soic_n), yyww is the date code, and xxxxxx is the lot code. a a dum1100br, adum1100br- 8 1 a du adu m m 1100ur, 1100ur-rl7 rl7 8 1 8 1 ad1100a r yyww* xxxxxx ad1100b r yyww* xxxxxx ad1100u r yyww* xxxxxx dum1100ar, adum1100ar-rl7 02462-003 figure 3. package branding
data sheet adum1100 rev. i | page 13 of 20 pin configuration and fu nction descriptions v dd1 1 1 v i 2 v dd1 1 3 gnd 1 4 v dd2 8 gnd 2 2 7 v o 6 gnd 2 2 5 adum1100 top view (not to scale) 02462-004 1 pin 1 and pin 3 are internally connected. either or both may be used for v dd1 . 2 pin 5 and pin 7 are internally connected. either or both may be used for gnd 2 . figure 4. pin configuration table 11. pin function descriptions pin o. neonic description 1 v dd1 input supply voltage, 3.0 v to 5.5 v. 2 v i logic input. 3 v dd1 input supply voltage, 3.0 v to 5.5 v. 4 gnd 1 input ground reference. 5 gnd 2 output ground reference. 6 v o logic output. 7 gnd 2 output ground reference. 8 v dd2 output supply voltage, 3.0 v to 5.5 v.
adum1100 data sheet rev. i | page 14 of 20 typical performance characteristics data rate (mbps) 20 0 current (ma) 18 16 2 0 25 50 75 100 125 150 14 12 10 8 6 4 5v 3.3v 02462-005 figure 5. typical input supply curr ent vs. logic signal frequency for 5 v and 3.3 v operation data rate (mbps) 0 0 25 50 75 100 125 150 02462-006 5 current (ma) 3 2 1 5v 3.3v 4 figure 6. typical output supply current vs. logic signal frequency for 5 v and 3.3 v operation temperature (c) 13 ?50 propagation delay (ns) 11 9 0 50 75 100 125 12 t phl ?25 25 t plh 10 02462-007 figure 7. typical propagation delays vs. temperature, 5 v operation 18 ?50 14 13 12 ?25 25 50 100 125 15 17 16 07 5 t phl t plh temperature (c) propagation delay (ns) 02462-008 figure 8. typical propagation delays vs. temperature, 3.3 v operation temperature (c) propagation delay (ns) 14 ?50 11 10 9 ?25 25 50 100 125 12 13 07 5 t phl t plh 02462-009 figure 9. typical propagation delays vs. temperature, 5 v/3 v operation 18 ?50 14 13 12 ?25 25 50 100 125 15 17 16 07 5 t phl t plh temperature (c) propagation delay (ns) 02462-010 figure 10. typical propagation delays vs. temperature, 3 v/5 v operation
data sheet adum1100 rev. i | page 15 of 20 1.7 3.0 1.3 1.2 1.1 3.5 4.0 4.5 5.0 5.5 1.4 1.6 1.5 ?40c +25c +125c input supply voltage, v dd1 (v) input threshold, v ith (v) 02462-011 figure 11. typical input voltage switching threshold, low-to-high transition input supply voltage, v dd1 (v) 1.4 3.0 input threshold, v ith (v) 1.0 0.9 0.8 3.5 4.0 4.5 5.0 5.5 1.1 1.3 1.2 ?40c +25c +125c 02462-012 figure 12. typical input voltage switching threshold, high-to-low transition
adum1100 data sheet rev. i | page 16 of 20 application information pc board layout the adum1100 digital isolator requires no external interface circuitry for the logic interfaces. a bypass capacitor is recom- mended at the input and output supply pins. the input bypass capacitor can conveniently be connected between pin 3 and pin 4 (see figure 13). alternatively, the bypass capacitor can be located between pin 1 and pin 4. the output bypass capacitor can be connected between pin 7 and pin 8 or pin 5 and pin 8. the capacitor value should be between 0.01 f and 0.1 f. the total lead length between both ends of the capacitor and the power supply pins should not exceed 20 mm. v dd1 v i (data in) gnd 1 v dd2 v o (data out) gnd 2 (optional) 02462-013 figure 13. recommended printed circuit board layout see the an-1109 application note for board layout guidelines. propagation delay-related parameters propagation delay time describes the length of time it takes for a logic signal to propagate through a component. propagation delay time to logic low output and propagation delay time to logic high output refer to the duration between an input signal transition and the respective output signal transition (see figure 14). input (v i ) output (v o ) t plh t phl 50% 50% 02462-014 figure 14. propagation delay parameters pulse width distortion is the maximum difference between t plh and t phl and provides an indication of how accurately the input signals timing is preserved in the components output signal. propagation delay skew is the difference between the minimum and maximum propagation delay values among multiple adum1100 components operated at the same operating temperature and having the same output load. depending on the input signal rise/fall time, the measured propagation delay based on the input 50% level can vary from the true propagation delay of the component (as measured from its input switching threshold). this is because the input threshold, as is the case with commonly used optocouplers, is at a different voltage level than the 50% point of typical input signals. this propagation delay difference is given by lh = t plh ? t plh = ( t r /0.8 v i )(0.5 v i ? v ith (l-h) ) hl = t phl ? t phl = ( t f /0.8 v i )(0.5 v i ? v ith (h-l) ) where: t plh and t phl are the propagation delays as measured from the input 50% level. t plh and t phl are the propagation delays as measured from the input switching thresholds. t r and t f are the input 10% to 90% rise/fall times. v i is the amplitude of the input signal (0 v to v i levels assumed). v ith (lC h) and v ith (hCl) are the input switching thresholds. ? lh v ith(h?l) input (v i ) v ith(l?h) v i ? hl t phl t' phl t plh t' plh output (v o ) 50% 50% 02462-015 figure 15. impact of input rise/fall time on propagation delay
data sheet adum1100 rev. i | page 17 of 20 input rise time (10%?90%, ns) 4 1 propagation delay change, ? lh (ns) 2 0 34 8 9 10 3 1 5v input signal 2 567 3.3v input signal 02462-016 figure 16. typical propagation delay change due to input rise time variation (for v dd1 = 3.3 v and 5 v) input rise time (10%?90%, ns) 0 1 propagation delay change, ? hl (ns) ?2 ?4 34 8 9 10 ?1 ?3 2567 02462-017 5v input signal 3.3v input signal figure 17. typical propagation delay change due to input fall time variation (for v dd1 = 3.3 v and 5 v) the impact of the slower input edge rates can also affect the measured pulse width distortion as based on the input 50% level. this impact can either increase or decrease the apparent pulse width distortion depending on the relative magnitudes of t phl , t plh , and pwd. the case of interest here is the condition that leads to the largest increase in pulse width distortion. the change in this case is given by pwd = pwd ? pwd = lh ? hl = ( t /0.8 v i )(v ? v ith ( l-h ) ? v ith ( h-l ) ), (for t = t r = t f ) where: pwd = | t plh ? t phl |. pwd = | t plh ? t phl |. this adjustment in pulse width distortion is plotted as a function of input rise/fall time in figure 18. input rise/fall time (10%?90%, ns) 6 1 pulse width distortion adjustment, ? pwd (ns) 0 34 8 9 10 2567 5 4 3 2 1 02462-018 3.3v input signal 5v input signal figure 18. typical pulse width distortion adjustment due to input rise/fall time variation (for v dd1 = 3.3 v and 5 v) method of operation, dc correctness, and magnetic field immunity the two coils in figure 1 act as a pulse transformer. positive and negative logic transitions at the isolator input cause narrow (2 ns) pulses to be sent via the transformer to the decoder. the decoder is bistable and therefore either set or reset by the pulses indicating input logic transitions. in the absence of logic transi- tions at the input for more than ~1 s, a periodic update pulse of the appropriate polarity is sent to ensure dc correctness at the output. if the decoder receives none of these update pulses for more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a logic high state by the watchdog timer circuit. the limitation on the magnetic field immunity of the adum1100 is set by the condition in which induced voltage in the transformers receiving coil is sufficiently large to either falsely set or reset the decoder. the analysis that follows defines the conditions under which this can occur. the 3.3 v operating condition of the adum1100 is examined because it represents the most susceptible mode of operation. the pulses at the transformer output are greater than 1.0 v in amplitude. the decoder has sensing thresholds at about 0.5 v, therefore establishing a 0.5 v margin in which induced voltages can be tolerated. the voltage induced across the receiving coil is given by v = (? d / dt ) ? r n 2 , n = 1, 2, . . . , n where: is the magnetic flux density (gauss). n is the number of turns in the receiving coil. r n is the radius of the nth turn in the receiving coil (cm).
adum1100 data sheet rev. i | page 18 of 20 given the geometry of the receiving coil in the adum1100 and an imposed requirement that the induced voltage be at most 50% of the 0.5 v margin at the decoder, a maximum allowable magnetic field is calculated, as shown in figure 19. magnetic field frequency (hz) 100 maximum allowable magnetic flux density (kgauss) 0.001 10 0.01 0.1 1 1k 10k 100k 1m 10m 100m 02462-019 figure 19. maximum allowable external magnetic field for example, at a magnetic field frequency of 1 mhz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 v at the receiving coil. this is about 50% of the sensing threshold and does not cause a faulty output transition. similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 v to 0.75 v, still well above the 0.5 v sensing threshold of the decoder. the preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the adum1100 transformers. figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. as can be seen, the adum1100 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. for the 1 mhz example noted, one would have to place a current of 0.5 ka 5 mm away from the adum1100 to affect the components operation. magnetic field frequency (hz) 1000 maximum allowable current (ka) 0.01 100 0.1 1 10 1k 10k 100k 1m 10m 100m 02462-020 distance = 1m distance = 100mm distance = 5mm figure 20. maximum allowable current for various current-to-adum1100 spacings note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. care should be taken in the layout of such traces to avoid this possibility. power consumption the supply current of the adum1100 isolator is a function of the supply voltage, the input data rate, and the output load. the input supply current is given by i ddi = i ddi ( q ) f 0.5 f r i ddi = i ddi (d) (2 f ? f r ) + i ddi (q) f > 0.5 f r the output supply current is given by i ddo = i ddo ( q ) f 0.5 f r i ddo = ( i ddo ( d ) + (0.5 10 ?3 ) c l v ddo ) (2 f ? f r ) + i ddo ( q ) f > 0.5 f r where: i ddi (d) , i ddo (d) are the input and output dynamic supply currents per channel (ma/mbps). c l is the output load capacitance (pf). v ddo is the output supply voltage (v). f is the input logic signal frequency (mhz, half the input data rate, nrz signaling). f r is the input stage refresh rate (mbps). i ddi (q) , i ddo (q) are the specified input and output quiescent supply currents (ma).
data sheet adum1100 rev. i | page 19 of 20 outline dimensions controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design. compliant to jedec standards ms-012-aa 012407-a 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 1.75 (0.0688) 1.35 (0.0532) seating plane 0.25 (0.0098) 0.10 (0.0040) 4 1 85 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 1.27 (0.0500) bsc 6.20 (0.2441) 5.80 (0.2284) 0.51 (0.0201) 0.31 (0.0122) coplanarity 0.10 figure 21. 8-lead standard small outline package [soic_n] narrow body (r-8) dimensions shown in millimeters and (inches) ordering guide model 1 temperature range maximum data rate (mbps) minimum pulse width (ns) package description package option adum1100ar ?40c to +105c 25 40 8-lead soic_n r-8 adum1100ar-rl7 ?40c to +105c 25 40 8-lead soic_n, 1,000 piece reel r-8 adum1100arz ?40c to +105c 25 40 8-lead soic_n r-8 adum1100arz-rl7 ?40c to +105c 25 40 8-lead soic_n, 1,000 piece reel r-8 adum1100br ?40c to +105c 100 10 8-lead soic_n r-8 adum1100br-rl7 ?40c to +105c 100 10 8-lead soic_n, 1,000 piece reel r-8 ADUM1100BRZ ?40c to +105c 100 10 8-lead soic_n r-8 ADUM1100BRZ-rl7 ?40c to +105c 100 10 8-lead soic_n, 1,000 piece reel r-8 adum1100ur ?40c to +125c 100 10 8-lead soic_n r-8 adum1100ur-rl7 ?40c to +125c 100 10 8-lead soic_n, 1,000 piece reel r-8 adum1100urz ?40c to +125c 100 10 8-lead soic_n r-8 adum1100urz-rl7 ?40c to +125c 100 10 8-lead soic_n, 1,000 piece reel r-8 1 z = rohs compliant part.
adum1100 data sheet rev. i | page 20 of 20 notes ?2001C2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d02462-0-3/12(i)

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